High-frequency micro-processors, and other computing engines, often use a clock grid (instead of a clock tree) as the global clock distribution mechanism to reduce clock uncertainty and make more of the nominal clock cycle available for computation.
On the one hand, when a clock tree is used for clock distribution, large parts of the global clock distribution network can be gated relatively easily, thereby largely eliminating global clock distribution (active/dynamic) power in a relatively local manner.
However, on the other hand clock grids are not easily gated when compared to clock trees, for purposes of power management. Although clock grids have a frequency advantage and hence a conceptual energy efficiency advantage when active, clock grids have some power draw backs when the micro-processor is inactive, such as, when waiting for information from memory without which the processor cannot continue. That is, power is consumed, in part, by the distribution of the clock and by the processor circuitry.
Clock grids rely on their being globally ‘on’ to reduce skew. Due to their configuration, traditional clock-gating is forced to clock-gate closer to the ‘leaves’ than is possible when using a clock tree. Since the grid typically has more capacitance and transistors than the corresponding spanning tree, more power potentially is consumed and/or wasted for circuits clocked by a clock grid. In such inactive situations, the global clock grid can consume hundreds of milliwatts even if all of the units are locally clock-gated, yet the processor still cannot make forward progress due to the nature of such a miss to memory or equivalent stalling condition.
In some situations, a clock grid may be managed using power management software control. For instance, for limited critical conditions, the active clock power of the clock grid is handled by using explicit software power-management instructions and sequences. For instance, power management through software control may be achieved by explicitly entering lower-power states under software control. The software controlled lower power states can gate the clock grid at the source.
However, a software controlled power management solution does not help with saving power under dynamic and/or critical conditions, as the software is unable to identify in a timely manner when the critical condition exists. For instance, a software controlled management solution is unable to determine when an instruction branch is going to mis-predict and then search for the proper instruction and/or data in lower level caches or the underlying memory system.